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> Ics chips: DM74LS73AN flip-flop negative-edge-triggered
Ics chips: DM74LS73AN flip-flop negative-edge-triggered
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
- This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs.
- The J and K data is processed by the flip-flops on the falling edge of
- The clock triggering occurs at a voltage level and is not directly related to the transition time of the
negative going edge of the clock pulse.
- The data on the J and K inputs is allowed to change while the clock is HIGH or LOW without affecting the outputs as long as setup and
- A low logic level on the clear
input will reset the outputs regardless of the levels of the
